The files and scripts needed for this example can be found in:
$AVT_TOOLS_DIR/tutorials/yagle/comb/ |
This example intends to illustrate the concepts previously described (functional abstraction mechanisms, VHDL|Verilog generation and timing back-annotation) and to give a first glance at Yagle's setup and execution modes.
This example is based on the combinational design below:
This design contains basic CMOS gates (nor, inverters, or) and a multiplexer based on pass-transistors. The design is described in the file comb.spi as a flat transistor netlist.
In order to perform the functional abstraction of the circuit, Yagle needs the following files:
The configuration set in the run.tcl script is sufficient to perform a first functional abstraction of COMB. The only variables that need to be set are the names of the alimentations (VDD and VSS). Lines preceded by a '#' are commented. We will see their meaning in the following sections. With this given configuration file, the tool is invoked as follow:
> run.tcl |
The steps of the functional abstraction process are displayed on the standard output. It should have this appearance:
This Yagle run generates two files:
It is also possible to generate a verilog file by adding the following line in the Tcl script:
avt_config avtOutputBehaviorFormat vlg |
As previously explained, the first step of the functional abstraction process is what is called disassembly. Disassembly is the partition of the original design into cones: it is the conversion of the netlist of non-oriented transistors into a netlist of oriented cones. In the basic execution mode, this netlist exists only as a data-structure in the program's memory, and is hidden from the user. It can be dumped on disk as an ASCII file by positioning the following variable in the Tcl script:
avt_config yagleGenerateConeFile yes |
The programs then generates a CNS file (Cone Netlist Structure): comb.cns. For disk saving purposes, this file is compact, and therefore quite uneasy to read. It is possible to obtain a more verbose file by positioning the avtVerboseCone variable to yes in the Tcl script. The programs will then generate a CNV file (Cone Netlist Verbose): comb.cnv.
Both files formats syntaxes are documented in the Yagle User Guide. Browsing the Cone Netlist Structure is far more convenient using the XYagle GUI.
> xyagle & |
Selecting the file comb.cns in the dialog box will lead open the following window:
For debugging purposes, it is also possible to disable the VHDL and Verilog generation. This can be done by positioning the following variable in the script:
avt_config YagleGenerateBehavior no |
Yagle will stop after the disassembly process.
In basic execution mode, the behavioral model (VHDL/Verilog) is generated without timing back-annotation. In order to perform this back-annotation, the first step is to include a technology file in the netlist to be abstracted. Here, we will use the file bsim4_dummy.hsp, which contains BSIM3 technology parameters of two models of transistors, named TN and TP.
avt_LoadFile ../techno/bsim4_dummy.hsp spice |
As explained in the timing back-annotation relevant section, timing back-annotation supports three levels of precision.
First level of precision:
In basic execution mode, the back-annotation is made with the first level of precision. Timing back-annotation is invoked by setting the following variable:
avt_config yagleTasTiming tdmin|tdmed|tdmax |
For CMOS DUAL cones, the tdmin, tdmed or tdmax directive selects the type of timing to be applied on the cone. For non-CMOS DUAL cones, this directive selects the type of timing to be applied on the up and down expressions of the cone.
Second level of precision:
This level is selected by setting the yagleSplitTimingRatio variable to a value V greater than one: if delays associated with up and down output transitions differ by a ratio greater than V, then up and down transitions are differentiated.
This variable allows to split the expression of the CMOS DUAL cones into up and down expressions, and to associate them minimum, average or maximum timing, according to the tdmin|tdmed|tdmax option.
Third level of precision:
This level is selected by setting the yagleSensitiveTimingRatio variable to a value V greater than one. For a given output transition (up or down), if delays associated with different input transitions differ by a ratio greater than V, then the delays are differentiated by input.